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Publication
Project
Honor
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Name: 余建政
Department: 修平科技大學 / 電子工程系 [elearning courses]
Research: 數位系統設計, VLSI設計, CPLD/FPGA電路設計, 智能控制
Office: B0408-4
Publication
Paper
1. 余建政, "Adaptive distributed BLS-FONTSM formation control for uncertain networking heterogeneous omnidirectional mobile multirobots [Journal of the Chinese Institute of Engineers]," , 2019.
2. 余建政, "Intelligent Adaptive Simultaneous Tracking and Stabilization Using Fuzzy Wavelet Networks for a Wheeled Inverted Pendulum [iRobotics]," , 2019.
3. 余建政, "Adaptive ORFWNN-Based Predictive PID Control [International Journal of Fuzzy Systems]," , 2019.
4. 余建政, "FIVE-TRANSISTOR SINGLE-PORT SRAM BIT CELL WITH HIGH SPEED AND LOW STANDBY CURRENT [International Journal of VLSI design & Communication Systems]," , 2018.
5. 余建政, "TwoTwo -Port SRAM Cell SRAM Cell SRAM Cell with Improved Improved Write Write Write Operation Operation [International Journal of Information and Electronics Engineering]," , 2018.
6. 余建政, "Adaptive Simultaneous Tracking and Stabilization Using DNA Algorithm for Uncertain Nonholonomic Mobile Robots [iRobotics]," , 2018.
7. 余建政, "A Laboratory Course on Mobile Robotics Education [iRobotics]," , 2018.
8. 余建政, "DUAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH LOW POWER CONSUMPTION [International Journal of Computer Science & Information Technology]," , 2018.
9. 余建政, "SINGLE-PORT FIVE-TRANSISTOR SRAM CELL WITH REDUCED LEAKAGE CURRENT IN STANDBY [International Journal of VLSI design & Communication Systems (VLSICS) ]," , 2017.
10. 余建政, "Five-Transistor SRAM Cell with Improved Write Capability [International Journal on Computer, Consumer and Control (IJ3C)]," , 2017.
11. 余建政, "5T SRAM Cell with Improved Read/Write-ability and Reduced Standby Leakage Current [IJCSI International Journal of Computer Science]," , 2016.
12. 余建政, "Design of High Performance Single-Port 5T SRAM Cell with Reduced Leakage Current [International Journal of Computer, Consumer and Control (IJ3C)]," , 2016.
13. 余建政, "Design of High Performance Single-Port 5T SRAM Cell [IOSR Journal of Electrical and Electronics Engineering (IOSR-JEEE)]," , 2016.
14. 余建政, "Single-Port Five-Transistor SRAM Cell with Reduced Leakage Current in Standby [International Journal of VLSI design & Communication Systems (VLSICS) ]," , 2016.
15. 余建政, "低功率CMOS雙邊緣觸發正反器的研究與設計 [修平學報]," , 2014.
16. 余建政, "藍芽智慧型火災警報通報系統之SoC設計 [修平學報第十期]," , 2005.
17. 余建政, "系統晶片設計中IPv4模組電路的功能驗證方法 [修平學報第九期,185-194頁]," , 2004.
18. 余建政, "基於嵌入式技術的儀器網路結構 [修平學報第九期,69-77頁]," , 2004.
19. 余建政, "5T SRAM Cell with Improved Read/Write-ability and Reduced Standby Leakage Current [IJCSI International Journal of Computer Science Issues],"
Domestic Paper
1. 余建政, "A New Single-Port Five-Transistor SRAM Cell Design for Signal Processing Systems [the 4th International Conference on Integrated Circuits and Microsystems (ICICM 2019)]," , 2019.
2. 余建政, "A Two-Port SRAM Cell with Improved Write-ability and Reduced Leakage Current for Signal Processing Applications [2019 IEEE 5th International Conference on Computer and Communications (ICCC 2019)]," , 2019.
3. 余建政, "5T單埠靜態隨機存取記憶體之設計 [2015 年民生電子研討會]," , 2016.
4. 余建政, "高效能7T雙埠靜態隨機存取記憶體設計 [2015光電與通訊工程研討會]," , 2015.
5. 余建政, "具高速讀取之5T SRAM [IETAC 2015]," , 2015.
6. 余建政, "具高速讀取之5T SRAM [IETAC 2015 第八屆資訊教育與科技應用研討會]," , 2015.
7. 余建政, "A Novel Design of Low-Power Double Edge-Triggered Flip-Flop [ICITES 2013]," , 2013.
8. 余建政, "A Novel Design of Low Power Double Edge-Triggered Flip-Flop [5th International Conference on BioMedical Engineering and Informatics (BMEI)]," , 2012.
9. 余建政, "Design of Low-Power Double Edge-Triggered Flip-Flop [The 2011 3rd International Conference on Information, Electronic and Computer Science]," , 2011.
10. 余建政, "Electrical Properties and leakage current Mechanisms of Bi3.2Gd0.8Ti3O12 Thin Films Prepared by a sol-gel method [Seventh International Conference on New Theories, Discoveries and Applications of Superconductors an]<," , 2009.
11. 余建政, "Low-Power Double Edge-Triggered Flip-Flop Circuit Design [3rd International Conference on Innovative Computing Information and Control (ICICIC-2008)]," , 2008.
12. 余建政, "Design of Low-Power Double Edge-Triggered Flip-Flop Circuit [2nd IEEE Conferecce on Industrial Electronics and Applications (ICIEA 2007)]," , 2007.
13. 余建政, "Design of Level Converter for Dual Voltage System in Very Low Power Application [ITC-CSCC 2005]," , 2005.
14. 余建政, "Design of Current-Mode Digital-to-Analog Converter in Hybrid Architecture [IEEE-NEWCAS’05]," , 2005.
15. 余建政, "Design of Low-Power Peak Voltage Detector Circuit [ITC-CSCC 2005]," , 2005.
16. 余建政, "DSP Embedded method for Electronic Instrument Network Design [The 8th World Multi-Conference on SYSTEMICS, CYBERNETICS AND INFORMATICS (SCI 2004)]," , 2004.
17. 余建政, "Study on Safety Model of Electronics Instrument with Embedded Technology [The 8th World Multi-Conference on SYSTEMICS, CYBERNETICS AND INFORMATICS (SCI 2004)]," , 2004.
18. 余建政, "Problem of Consistency Checking in Mixed-Signal SoC with IP Co-Design [The Eighth International Conference on Computer Supported Cooperative Work in Design (CSCWD 2004)]," , 2004.
19. 余建政, "Security Approach Used for Instrument Control over Internet [The Eighth International Conference on Computer Supported Cooperative Work in Design (CSCWD 2004)]," , 2004.
20. 余建政, "Design of High Performance CMOS Current-Mode Winner-Take-All Circuit [The 5th International Conference On ASIC (ASICON'03)]," , 2003.
21. 余建政, "”Design of High Performance CMOS Current-Mode Winn [The 5th International Conference On ASIC (ASICON'0]," , 2003.
22. 余建政, "The application of a simple neural network for fault diagnosis system [4th IASTED International Conferences on Signal and Image Processing]," , 2002.
23. 余建政, "Optimization of the Backpropagation Algorithm for Training Feedforward Neural Networks [International Symposium on Nonlinear Theory and its Applications (NOLTA'2002)]," , 2002.
24. 余建政, "A Static Power-Saving CMOS Level Converter for Dual Supply Voltages [International Symposium on Nonlinear Theory and its Applications]," , 2002.
25. 余建政, "Research on Emissions Trading Among Separate Generation Systems [International Symposium on Nonlinear Theory and its Applications (NOLTA'2002)]," , 2002.
26. 余建政, "An Efficient Backpropagation Learning Algorithm for Pattern Recognition [nternational Symposium on Artificial Intelligence and Applications]," , 2002.
27. 余建政, "A backpropagation algorithm with adaptive learning rate and momentum coefficient [International Conferences on Neural Networks (IJCNN 2002)]," , 2002.
28. 余建政, "The Estimation of Harmonic Contents of a Single Phase Transformer by Harmonic Describing Functions [International Symposium on Nonlinear Theory and its Applications (NOLTA'2002)]," , 2002.
29. 余建政, "To Estimate Transient Exciting Current of Current Transformers by Dual-input and Transient Describing Functions [International Symposium on Nonlinear Theory and its Applications (NOLTA'2002)]," , 2002.
30. 余建政, "An adaptive activation function for multilayer feedforward neural networks [The IEEE Region 10 Technical Conference on Computer, Communication, Control and Power Ingineering (]," , 2002.
31. 余建政, "Economic Dispatch of Power Transmission Losses Minimization By Penalty-Function Nonlinear Programming Neural Network Method [International Symposium on Nonlinear Theory and its Applications (NOLTA'2002)]," , 2002.
32. 余建政, "A Simple Procedure in Back-propagation Training [International Conferences on Info-tech & Info-net (ICII 2001)]," , 2001.
33. 余建政, "To Improve the Training Time of BP Neural Networks [International Conferences on Info-tech & Info-net (ICII 2001)]," , 2001.
34. 余建政, "A New Level Converter for Low-Power Applications [2001 IEEE International Symposium on Circuits and Systems]," , 2001.
35. 余建政, "A 3-input XOR/XNOR for Low-Voltage Low-Power Applications [IEEE Asia Pacific Conference on CAS]," , 2000.
36. 余建政, "A Error-Correction Learning Algorithm to Improve Perceptron Capabilities [IASTED International Conference on Control and Applications (CA'99)]," , 1999.
37. 余建政, "A Generalized Block Distribution Algorithm for Fast Carry Skip Adder Design [IEEE Conference on Multimedia Technology for Asia-Pacific Information Infrastructure]," , 1999.
38. 余建政, "Design of Minimum Power-Delay Product CMOS Adder [IASTED International Conference on Modelling and Simulation (MS'99)]," , 1999.
Honor
1. ICCC 2019 (2019-12)
2. 2019首爾國際發明展 (2019-11)
3. 2019首爾國際發明展 (2019-11)
4. 2019第十屆IIIC國際創新發明競賽 (2019-11)
5. 2019第十屆IIIC國際創新發明競賽 (2019-11)
6. 2019第十屆IIIC國際創新發明競賽 (2019-11)
7. 2019第7屆澳門國際創新發明展 (2019-10)
8. 2019第7屆澳門國際創新發明展 (2019-10)
9. 2019馬來西亞國際發明展 (2019-05)
10. 2019馬來西亞國際發明展 (2019-05)
11. 2019馬來西亞國際發明展 (2019-05)
12. 2019馬來西亞國際發明展 (2019-05)
13. 2018全國電腦輔助電路板設計技能競賽 (2018-12)
14. 2018年首爾國際發明展 (2018-12)
15. 2018首爾國際發明展 (2018-12)
16. 2018年首爾國際發明展 (2018-12)
17. 2018首爾國際發明展 (2018-12)
18. 2018香港國際發明展 (2018-12)
19. 2018香港國際發明展 (2018-12)
20. 2018香港國際發明展 (2018-12)
21. 2018第29屆馬來西亞ITEX國際發明展 (2018-05)
22. 2018年馬來西亞國際發明展 (2018-05)
23. 2018第29屆馬來西亞ITEX國際發明展 (2018-05)
24. 2018年馬來西亞國際發明展 (2018-05)
25. 2018第29屆馬來西亞ITEX國際發明展 (2018-05)
26. 2018阿基米德國際發明展 (2018-04)
27. 2017全國電腦輔助電路板設計技能競賽 (2017-12)
28. 2017香港創新科技國際發明展 (2017-12)
29. 2017香港創新科技國際發明展 (2017-12)
30. 2017香港創新科技國際發明展 (2017-12)
31. 2017韓國首爾國際發明展 (2017-12)
32. 2017韓國首爾國際發明展 (2017-12)
33. 2018第29屆馬來西亞ITEX國際發明展 (2017-12)
34. 2017第28屆馬來西亞ITEX國際發明展 (2017-05)
35. 2017第28屆馬來西亞ITEX國際發明展 (2017-05)
36. 2017第28屆馬來西亞ITEX國際發明展 (2017-05)
37. 2016全國電腦輔助電路板設計技能競賽 (2016-12)
38. 2016韓國首爾國際發明展 (2016-12)
39. 2016韓國首爾國際發明展 (2016-12)
40. 2016年首爾國際發明展 (2016-12)
41. 2016年德國紐倫堡國際發明展 (2016-10)
42. 2016馬來西亞發明展 (2016-05)
43. 第十一屆數位訊號處理創思設計競賽 (2016-03)
44. 2015全國電腦輔助電路板設計技能競賽 (2015-12)
45. 2015年首爾國際發明展 (2015-11)
46. 2015年首爾國際發明展 (2015-11)
47. 2015台北發明展 (2015-10)
48. 2015台北發明展 (2015-10)
49. 2015馬來西亞國際發明展 (2015-05)
50. iLMS課程教材使用指數 (2015-02)
51. iLMS課程作業繳交使用指數高使用率教師 (2015-02)
52. 2014全國電腦輔助電路板設計技能競賽 (2014-11)
53. 2014年台北國際發明暨技術交易展 (2014-09)
54. 2013全國電腦輔助電路板設計技能競賽 (2013-11)
55. 家弘學術研究優良人員 (2007-12)
56. 資深優良教師 (2004-08)